00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028 ;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
00029 ;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte
00030 ; Numbers in brackets are clocks counted from center of last sync bit
00031 ; when instruction starts
00032
00033 ;----------------------------------------------------------------------------
00034 ; order of registers pushed:
00035 ; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4
00036 ;----------------------------------------------------------------------------
00037 USB_INTR_VECTOR:
00038 push YL ;2 push only what is necessary to sync with edge ASAP
00039 in YL, SREG ;1
00040 push YL ;2
00041 ;----------------------------------------------------------------------------
00042 ; Synchronize with sync pattern:
00043 ;
00044 ; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
00045 ; sync up with J to K edge during sync pattern -- use fastest possible loops
00046 ; first part has no timeout because it waits for IDLE or SE1 (== disconnected)
00047 ;-------------------------------------------------------------------------------
00048 waitForJ: ;-
00049 sbis USBIN, USBMINUS ;1 <-- sample: wait for D- == 1
00050 rjmp waitForJ ;2
00051 ;-------------------------------------------------------------------------------
00052 ; The following code results in a sampling window of < 1/4 bit
00053 ; which meets the spec.
00054 ;-------------------------------------------------------------------------------
00055 waitForK: ;-
00056 sbis USBIN, USBMINUS ;1 [00] <-- sample
00057 rjmp foundK ;2 [01]
00058 sbis USBIN, USBMINUS ; <-- sample
00059 rjmp foundK
00060 sbis USBIN, USBMINUS ; <-- sample
00061 rjmp foundK
00062 sbis USBIN, USBMINUS ; <-- sample
00063 rjmp foundK
00064 sbis USBIN, USBMINUS ; <-- sample
00065 rjmp foundK
00066 sbis USBIN, USBMINUS ; <-- sample
00067 rjmp foundK
00068 #if USB_COUNT_SOF
00069 lds YL, usbSofCount
00070 inc YL
00071 sts usbSofCount, YL
00072 #endif
00073 rjmp sofError
00074 ;------------------------------------------------------------------------------
00075 ; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for
00076 ; center sampling]
00077 ; we have 1 bit time for setup purposes, then sample again.
00078 ; Numbers in brackets are cycles from center of first sync (double K)
00079 ; bit after the instruction
00080 ;------------------------------------------------------------------------------
00081 foundK: ;- [02]
00082 lds YL, usbInputBufOffset;2 [03+04] tx loop
00083 push YH ;2 [05+06]
00084 clr YH ;1 [07]
00085 subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init]
00086 sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init]
00087 push shift ;2 [10+11]
00088 ser shift ;1 [12]
00089 sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early)
00090 rjmp haveTwoBitsK ;2 [00] [14]
00091 pop shift ;2 [15+16] undo the push from before
00092 pop YH ;2 [17+18] undo the push from before
00093 rjmp waitForK ;2 [19+20] this was not the end of sync, retry
00094 ; The entire loop from waitForK until rjmp waitForK above must not exceed two
00095 ; bit times (= 20 cycles).
00096
00097 ;----------------------------------------------------------------------------
00098 ; push more registers and initialize values while we sample the first bits:
00099 ;----------------------------------------------------------------------------
00100 haveTwoBitsK: ;- [01]
00101 push x1 ;2 [02+03]
00102 push x2 ;2 [04+05]
00103 push x3 ;2 [06+07]
00104 push bitcnt ;2 [08+09]
00105 in x1, USBIN ;1 [00] [10] <-- sample bit 0
00106 bst x1, USBMINUS ;1 [01]
00107 bld shift, 0 ;1 [02]
00108 push cnt ;2 [03+04]
00109 ldi cnt, USB_BUFSIZE ;1 [05]
00110 push x4 ;2 [06+07] tx loop
00111 rjmp rxLoop ;2 [08]
00112 ;----------------------------------------------------------------------------
00113 ; Receiver loop (numbers in brackets are cycles within byte after instr)
00114 ;----------------------------------------------------------------------------
00115 unstuff0: ;- [07] (branch taken)
00116 andi x3, ~0x01 ;1 [08]
00117 mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit
00118 in x2, USBIN ;1 [00] [10] <-- sample bit 1 again
00119 andi x2, USBMASK ;1 [01]
00120 breq se0Hop ;1 [02] SE0 check for bit 1
00121 ori shift, 0x01 ;1 [03] 0b00000001
00122 nop ;1 [04]
00123 rjmp didUnstuff0 ;2 [05]
00124 ;-----------------------------------------------------
00125 unstuff1: ;- [05] (branch taken)
00126 mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit
00127 andi x3, ~0x02 ;1 [07]
00128 ori shift, 0x02 ;1 [08] 0b00000010
00129 nop ;1 [09]
00130 in x1, USBIN ;1 [00] [10] <-- sample bit 2 again
00131 andi x1, USBMASK ;1 [01]
00132 breq se0Hop ;1 [02] SE0 check for bit 2
00133 rjmp didUnstuff1 ;2 [03]
00134 ;-----------------------------------------------------
00135 unstuff2: ;- [05] (branch taken)
00136 andi x3, ~0x04 ;1 [06]
00137 ori shift, 0x04 ;1 [07] 0b00000100
00138 mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit
00139 nop ;1 [09]
00140 in x2, USBIN ;1 [00] [10] <-- sample bit 3
00141 andi x2, USBMASK ;1 [01]
00142 breq se0Hop ;1 [02] SE0 check for bit 3
00143 rjmp didUnstuff2 ;2 [03]
00144 ;-----------------------------------------------------
00145 unstuff3: ;- [00] [10] (branch taken)
00146 in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late
00147 andi x2, USBMASK ;1 [02]
00148 breq se0Hop ;1 [03] SE0 check for stuffed bit 3
00149 andi x3, ~0x08 ;1 [04]
00150 ori shift, 0x08 ;1 [05] 0b00001000
00151 rjmp didUnstuff3 ;2 [06]
00152 ;----------------------------------------------------------------------------
00153 ; extra jobs done during bit interval:
00154 ;
00155 ; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs],
00156 ; overflow check, jump to the head of rxLoop
00157 ; bit 1: SE0 check
00158 ; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long]
00159 ; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long]
00160 ; bit 4: SE0 check, none
00161 ; bit 5: SE0 check, none
00162 ; bit 6: SE0 check, none
00163 ; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others
00164 ;----------------------------------------------------------------------------
00165 rxLoop: ;- [09]
00166 in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed)
00167 andi x2, USBMASK ;1 [01]
00168 brne SkipSe0Hop ;1 [02]
00169 se0Hop: ;- [02]
00170 rjmp se0 ;2 [03] SE0 check for bit 1
00171 SkipSe0Hop: ;- [03]
00172 ser x3 ;1 [04]
00173 andi shift, 0xf9 ;1 [05] 0b11111001
00174 breq unstuff0 ;1 [06]
00175 didUnstuff0: ;- [06]
00176 eor x1, x2 ;1 [07]
00177 bst x1, USBMINUS ;1 [08]
00178 bld shift, 1 ;1 [09]
00179 in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed)
00180 andi x1, USBMASK ;1 [01]
00181 breq se0Hop ;1 [02] SE0 check for bit 2
00182 andi shift, 0xf3 ;1 [03] 0b11110011
00183 breq unstuff1 ;1 [04] do remaining work for bit 1
00184 didUnstuff1: ;- [04]
00185 eor x2, x1 ;1 [05]
00186 bst x2, USBMINUS ;1 [06]
00187 bld shift, 2 ;1 [07]
00188 nop2 ;2 [08+09]
00189 in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed)
00190 andi x2, USBMASK ;1 [01]
00191 breq se0Hop ;1 [02] SE0 check for bit 3
00192 andi shift, 0xe7 ;1 [03] 0b11100111
00193 breq unstuff2 ;1 [04]
00194 didUnstuff2: ;- [04]
00195 eor x1, x2 ;1 [05]
00196 bst x1, USBMINUS ;1 [06]
00197 bld shift, 3 ;1 [07]
00198 didUnstuff3: ;- [07]
00199 andi shift, 0xcf ;1 [08] 0b11001111
00200 breq unstuff3 ;1 [09]
00201 in x1, USBIN ;1 [00] [10] <-- sample bit 4
00202 andi x1, USBMASK ;1 [01]
00203 breq se0Hop ;1 [02] SE0 check for bit 4
00204 eor x2, x1 ;1 [03]
00205 bst x2, USBMINUS ;1 [04]
00206 bld shift, 4 ;1 [05]
00207 didUnstuff4: ;- [05]
00208 andi shift, 0x9f ;1 [06] 0b10011111
00209 breq unstuff4 ;1 [07]
00210 nop2 ;2 [08+09]
00211 in x2, USBIN ;1 [00] [10] <-- sample bit 5
00212 andi x2, USBMASK ;1 [01]
00213 breq se0 ;1 [02] SE0 check for bit 5
00214 eor x1, x2 ;1 [03]
00215 bst x1, USBMINUS ;1 [04]
00216 bld shift, 5 ;1 [05]
00217 didUnstuff5: ;- [05]
00218 andi shift, 0x3f ;1 [06] 0b00111111
00219 breq unstuff5 ;1 [07]
00220 nop2 ;2 [08+09]
00221 in x1, USBIN ;1 [00] [10] <-- sample bit 6
00222 andi x1, USBMASK ;1 [01]
00223 breq se0 ;1 [02] SE0 check for bit 6
00224 eor x2, x1 ;1 [03]
00225 bst x2, USBMINUS ;1 [04]
00226 bld shift, 6 ;1 [05]
00227 didUnstuff6: ;- [05]
00228 cpi shift, 0x02 ;1 [06] 0b00000010
00229 brlo unstuff6 ;1 [07]
00230 nop2 ;2 [08+09]
00231 in x2, USBIN ;1 [00] [10] <-- sample bit 7
00232 andi x2, USBMASK ;1 [01]
00233 breq se0 ;1 [02] SE0 check for bit 7
00234 eor x1, x2 ;1 [03]
00235 bst x1, USBMINUS ;1 [04]
00236 bld shift, 7 ;1 [05]
00237 didUnstuff7: ;- [05]
00238 cpi shift, 0x04 ;1 [06] 0b00000100
00239 brlo unstuff7 ;1 [07]
00240 eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others
00241 nop ;1 [09]
00242 in x1, USBIN ;1 [00] [10] <-- sample bit 0
00243 st y+, x3 ;2 [01+02] store data
00244 eor x2, x1 ;1 [03]
00245 bst x2, USBMINUS ;1 [04]
00246 bld shift, 0 ;1 [05]
00247 subi cnt, 1 ;1 [06]
00248 brcs overflow ;1 [07]
00249 rjmp rxLoop ;2 [08]
00250 ;-----------------------------------------------------
00251 unstuff4: ;- [08]
00252 andi x3, ~0x10 ;1 [09]
00253 in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4
00254 andi x1, USBMASK ;1 [01]
00255 breq se0 ;1 [02] SE0 check for stuffed bit 4
00256 ori shift, 0x10 ;1 [03]
00257 rjmp didUnstuff4 ;2 [04]
00258 ;-----------------------------------------------------
00259 unstuff5: ;- [08]
00260 ori shift, 0x20 ;1 [09]
00261 in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5
00262 andi x2, USBMASK ;1 [01]
00263 breq se0 ;1 [02] SE0 check for stuffed bit 5
00264 andi x3, ~0x20 ;1 [03]
00265 rjmp didUnstuff5 ;2 [04]
00266 ;-----------------------------------------------------
00267 unstuff6: ;- [08]
00268 andi x3, ~0x40 ;1 [09]
00269 in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6
00270 andi x1, USBMASK ;1 [01]
00271 breq se0 ;1 [02] SE0 check for stuffed bit 6
00272 ori shift, 0x40 ;1 [03]
00273 rjmp didUnstuff6 ;2 [04]
00274 ;-----------------------------------------------------
00275 unstuff7: ;- [08]
00276 andi x3, ~0x80 ;1 [09]
00277 in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7
00278 andi x2, USBMASK ;1 [01]
00279 breq se0 ;1 [02] SE0 check for stuffed bit 7
00280 ori shift, 0x80 ;1 [03]
00281 rjmp didUnstuff7 ;2 [04]
00282
00283 macro POP_STANDARD ; 16 cycles
00284 pop x4
00285 pop cnt
00286 pop bitcnt
00287 pop x3
00288 pop x2
00289 pop x1
00290 pop shift
00291 pop YH
00292 endm
00293 macro POP_RETI ; 5 cycles
00294 pop YL
00295 out SREG, YL
00296 pop YL
00297 endm
00298
00299 #include "asmcommon.inc"
00300
00301 ;---------------------------------------------------------------------------
00302 ; USB spec says:
00303 ; idle = J
00304 ; J = (D+ = 0), (D- = 1)
00305 ; K = (D+ = 1), (D- = 0)
00306 ; Spec allows 7.5 bit times from EOP to SOP for replies
00307 ;---------------------------------------------------------------------------
00308 bitstuffN: ;- [04]
00309 eor x1, x4 ;1 [05]
00310 clr x2 ;1 [06]
00311 nop ;1 [07]
00312 rjmp didStuffN ;1 [08]
00313 ;---------------------------------------------------------------------------
00314 bitstuff6: ;- [04]
00315 eor x1, x4 ;1 [05]
00316 clr x2 ;1 [06]
00317 rjmp didStuff6 ;1 [07]
00318 ;---------------------------------------------------------------------------
00319 bitstuff7: ;- [02]
00320 eor x1, x4 ;1 [03]
00321 clr x2 ;1 [06]
00322 nop ;1 [05]
00323 rjmp didStuff7 ;1 [06]
00324 ;---------------------------------------------------------------------------
00325 sendNakAndReti: ;- [-19]
00326 ldi x3, USBPID_NAK ;1 [-18]
00327 rjmp sendX3AndReti ;1 [-17]
00328 ;---------------------------------------------------------------------------
00329 sendAckAndReti: ;- [-17]
00330 ldi cnt, USBPID_ACK ;1 [-16]
00331 sendCntAndReti: ;- [-16]
00332 mov x3, cnt ;1 [-15]
00333 sendX3AndReti: ;- [-15]
00334 ldi YL, 20 ;1 [-14] x3==r20 address is 20
00335 ldi YH, 0 ;1 [-13]
00336 ldi cnt, 2 ;1 [-12]
00337 ; rjmp usbSendAndReti fallthrough
00338 ;---------------------------------------------------------------------------
00339 ;usbSend:
00340 ;pointer to data in 'Y'
00341 ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
00342 ;uses: x1...x4, btcnt, shift, cnt, Y
00343 ;Numbers in brackets are time since first bit of sync pattern is sent
00344 ;We need not to match the transfer rate exactly because the spec demands
00345 ;only 1.5% precision anyway.
00346 usbSendAndReti: ;- [-13] 13 cycles until SOP
00347 in x2, USBDDR ;1 [-12]
00348 ori x2, USBMASK ;1 [-11]
00349 sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups)
00350 in x1, USBOUT ;1 [-08] port mirror for tx loop
00351 out USBDDR, x2 ;1 [-07] <- acquire bus
00352 ; need not init x2 (bitstuff history) because sync starts with 0
00353 ldi x4, USBMASK ;1 [-06] exor mask
00354 ldi shift, 0x80 ;1 [-05] sync byte is first byte sent
00355 ldi bitcnt, 6 ;1 [-04]
00356 txBitLoop: ;- [-04] [06]
00357 sbrs shift, 0 ;1 [-03] [07]
00358 eor x1, x4 ;1 [-02] [08]
00359 ror shift ;1 [-01] [09]
00360 didStuffN: ;- [09]
00361 out USBOUT, x1 ;1 [00] [10] <-- out N
00362 ror x2 ;1 [01]
00363 cpi x2, 0xfc ;1 [02]
00364 brcc bitstuffN ;1 [03]
00365 dec bitcnt ;1 [04]
00366 brne txBitLoop ;1 [05]
00367 sbrs shift, 0 ;1 [06]
00368 eor x1, x4 ;1 [07]
00369 ror shift ;1 [08]
00370 didStuff6: ;- [08]
00371 nop ;1 [09]
00372 out USBOUT, x1 ;1 [00] [10] <-- out 6
00373 ror x2 ;1 [01]
00374 cpi x2, 0xfc ;1 [02]
00375 brcc bitstuff6 ;1 [03]
00376 sbrs shift, 0 ;1 [04]
00377 eor x1, x4 ;1 [05]
00378 ror shift ;1 [06]
00379 ror x2 ;1 [07]
00380 didStuff7: ;- [07]
00381 ldi bitcnt, 6 ;1 [08]
00382 cpi x2, 0xfc ;1 [09]
00383 out USBOUT, x1 ;1 [00] [10] <-- out 7
00384 brcc bitstuff7 ;1 [01]
00385 ld shift, y+ ;2 [02+03]
00386 dec cnt ;1 [04]
00387 brne txBitLoop ;1 [05]
00388 makeSE0:
00389 cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles]
00390 lds x2, usbNewDeviceAddr;2 [07+08]
00391 lsl x2 ;1 [09] we compare with left shifted address
00392 ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
00393 ;set address only after data packet was sent, not after handshake
00394 out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle
00395 subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3
00396 sbci YH, 0 ;1 [02]
00397 breq skipAddrAssign ;1 [03]
00398 sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer
00399 ;----------------------------------------------------------------------------
00400 ;end of usbDeviceAddress transfer
00401 skipAddrAssign: ;- [03/04]
00402 ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [05] int0 occurred during TX -- clear pending flag
00403 USB_STORE_PENDING(x2) ;1 [06]
00404 ori x1, USBIDLE ;1 [07]
00405 in x2, USBDDR ;1 [08]
00406 cbr x2, USBMASK ;1 [09] set both pins to input
00407 mov x3, x1 ;1 [10]
00408 cbr x3, USBMASK ;1 [11] configure no pullup on both pins
00409 ldi x4, 3 ;1 [12]
00410 se0Delay: ;- [12] [15]
00411 dec x4 ;1 [13] [16]
00412 brne se0Delay ;1 [14] [17]
00413 nop2 ;2 [18+19]
00414 out USBOUT, x1 ;1 [20] <--out J (idle) -- end of SE0 (EOP sig.)
00415 out USBDDR, x2 ;1 [21] <--release bus now
00416 out USBOUT, x3 ;1 [22] <--ensure no pull-up resistors are active
00417 rjmp doReturn ;1 [23]
00418 ;---------------------------------------------------------------------------
